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ADP3120A Dual Bootstrapped, 12 V MOSFET Driver with Output Disable
The ADP3120A is a single Phase 12 V MOSFET gate drivers optimized to drive the gates of both high-side and low-side power MOSFETs in a synchronous buck converter. The high-side and low-side driver is capable of driving a 3000 pF load with a 45 ns propagation delay and a 25 ns transition time. With a wide operating voltage range, high or low side MOSFET gate drive voltage can be optimized for the best efficiency. Internal adaptive nonoverlap circuitry further reduces switching losses by preventing simultaneous conduction of both MOSFETs. The floating top driver design can accommodate VBST voltages as high as 35 V, with transient voltages as high as 40 V. Both gate outputs can be driven low by applying a low logic level to the Output Disable (OD) pin. An Undervoltage Lockout function ensures that both driver outputs are low when the supply voltage is low, and a Thermal Shutdown function provides the IC with overtemperature protection.
Features http://onsemi.com MARKING DIAGRAMS
8 8 1 SO-8 D SUFFIX CASE 751 3120A ALYW G 1 1 L3C ALYWG G 8
1 A L Y W G
DFN8 MN SUFFIX CASE 506BJ
* * * * * *
All-In-One Synchronous Buck Driver Bootstrapped High-Side Drive One PWM Signal Generates Both Drives Anticross Conduction Protection Circuitry OD for Disabling the Driver Outputs Meets CPU VR Requirement when Used with Patented FlexModet Controller These are Pb-Free Devices
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
PIN CONNECTIONS
BST IN OD VCC 1 BST IN OD VCC (Top View) 8 DRVH SWN PGND DRVL 1 8 DRVH SWN PGND DRVL
Applications
* Multiphase Desktop CPU Supplies * Single-Supply Synchronous Buck Converters
ORDERING INFORMATION
Device ADP3120AJRZ ADP3120AJRZ-RL ADP3120AJCPZ-RL Package SO-8 (Pb-Free) Shipping 98 Units / Rail
SO-8 2500 Tape & Reel (Pb-Free) DFN8 5000 Tape & Reel (Pb-Free)
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2008
August, 2008 - Rev. 3
1
Publication Order Number: ADP3120A/D
ADP3120A
OD 3 VCC TSD UVLO IN 2 8 DRVH 1 BST
FALLING EDGE DELAY FALLING EDGE DELAY START STOP NON-OVERLAP TIMERS
MONITOR 7 SWN
MONITOR
MIN DRVL OFF TIMER
4 5 6
VCC DRVL PGND
Figure 1. Block Diagram
PIN DESCRIPTION
SO-8 1 DFN8 1 Symbol BST Description Upper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and SW pins holds this bootstrap voltage for the high-side MOSFET as it is switched. The recommended capacitor value is between 100 nF and 1.0 mF. An external diode is required with the ADP3120A. Logic-Level Input. This pin has primary control of the drive outputs. Output Disable. When low, normal operation is disabled forcing DRVH and DRVL low. Input Supply. A 1.0 mF ceramic capacitor should be connected from this pin to PGND. Output drive for the lower MOSFET. Power Ground. Should be closely connected to the source of the lower MOSFET. Switch Node. Connect to the source of the upper MOSFET. Output drive for the upper MOSFET.
2 3 4 5 6 7 8
2 3 4 5 6 7 8
IN OD VCC DRVL PGND SWN DRVH
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ADP3120A
MAXIMUM RATINGS
Rating Operating Ambient Temperature, TA Operating Junction Temperature, TJ (Note 1) Package Thermal Resistance: SO-8 Junction-to-Case, RqJC Junction-to-Ambient, RqJA (2-Layer Board) Package Thermal Resistance: DFN8 (Note 2) Junction-to-Case, RqJC (From die to exposed pad) Junction-to-Ambient, RqJA Storage Temperature Range, TS Lead Temperature Soldering (10 sec): Reflow (SMD styles only) JEDEC Moisture Sensitivity Level Pb-Free (Note 3) SO-8 (260 peak profile) Value 0 to 85 0 to 150 45 123 7.5 55 -65 to 150 260 peak 1 Unit C C C/W C/W C/W C/W C C -
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Internally limited by thermal shutdown, 150C min. 2. 2 layer board, 1 in2 Cu, 1 oz thickness. 3. 60-180 seconds minimum above 237C. NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
MAXIMUM RATINGS
Pin Symbol VCC PGND BST Pin Name Main Supply Voltage Input Ground Bootstrap Supply Voltage Input VMAX 15 V 0V 35 V wrt/PGND 40 V < 50 ns wrt/PGND 15 V wrt/SW 35 V 40 V < 50 ns BST + 0.3 V VCC + 0.3 V 6.5 V 6.5 V VMIN -0.3 V 0V -0.3 V wrt/SW
SW DRVH DRVL IN OD NOTE:
Switching Node (Bootstrap Supply Return) High-Side Driver Output Low-Side Driver Output DRVH and DRVL Control Input Output Disable
-5.0 V -10 V < 200 ns -0.3 V wrt/SW -2.0 V < 200 ns wrt/SW -0.3 V DC -5.0 V < 200 ns -0.3 V -0.3 V
All voltages are with respect to PGND except where noted.
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ADP3120A
ELECTRICAL CHARACTERISTICS (Note 4) (VCC = 12 V, TA = 0C to +85C, TJ = 0C to +125C unless otherwise noted.)
Characteristic Supply Supply Voltage Range Supply Current OD Input Input Voltage High Input Voltage Low Hysteresis Input Current PWM Input Input Voltage High Input Voltage Low Hysteresis Input Current High-Side Driver Output Resistance, Sourcing Current Output Resistance, Sinking Current Output Resistance, Unbiased Transition Times Propagation Delay Times (Note 5) - - - trDRVH tfDRVH tpdhDRVH tpdlDRVH tpdlOD tpdhOD SW Pulldown Resitance Low-Side Driver Output Resistance, Sourcing Current Output Resistance, Sinking Current Output Resistance, Unbiased Transition Times Propagation Delay Times (Note 5) - - - trDRVL tfDRVL tpdhDRVL tpdlDRVL tpdlOD tpdhOD Timeout Delay Undervoltage Lockout UVLO Startup UVLO Shutdown Hysteresis - - - - - - 3.9 3.7 0.1 4.3 4.1 0.2 4.5 4.3 0.4 V V V - TA = 0 C to 85 C TA = 25 C TA = 0 C to 85 C TA = 25 C VCC = PGND CLOAD = 3.0 nF, (See Figure 3) CLOAD = 3.0 nF, (See Figure 3) (Note 6, tpdhDRVL only) (See Figure 2) (See Figure 2) DRVH - SW = 0 - - - - - - 1.8 - 1.0 - 15 16 11 12 15 20 20 85 3.9 3.3 2.6 1.8 - 35 30 35 45 35 35 - ns W W kW ns ns - BST - SW = 12 V; TA = 0 C to 85 C BST - SW = 12 V; TA = 25 C BST - SW = 12 V; TA = 0 C to 85 C BST - SW = 12 V; TA = 25 C BST - SW = 0 V BST - SW = 12 V, CLOAD = 3.0 nF (See Figure 3) BST - SW = 12 V, CLOAD = 3.0 nF (See Figure 3) BST - SW = 12 V, CLOAD = 3.0 nF (See Figure 3) (See Figure 2) (See Figure 2) SW to PGND - - - - - 32 2.2 - 1.0 - 15 20 11 45 25 20 25 15 3.9 3.3 2.6 1.8 - 40 30 70 35 35 55 - kW W W kW ns ns VPWM_HI VPWM_LO - - - - - No internal pullup or pulldown resistors 2.0 - - -1.0 - - 400 - - 0.8 - +1.0 V V mV mA VOD_HI VOD_LO - - - No internal pullup or pulldown resistors 2.0 - - -1.0 - - 400 - - 0.8 - +1.0 V V mV mA VCC ISYS - BST = 12 V, IN = 0 V 4.6 - - 0.7 13.2 5.0 V mA Symbol Condition Min Typ Max Unit
4. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC). 5. For propagation delays, "tpdh" refers to the specified signal going high; "tpdl" refers to it going low. 6. Guaranteed by design; not tested in production.
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ADP3120A
APPLICATIONS INFORMATION
Theory of Operation
The ADP3120A are single phase MOSFET drivers designed for driving two N-channel MOSFETs in a synchronous buck converter topology. The ADP3120A will operate from 5.0 V or 12 V, but have been optimized for high current multi-phase buck regulators that convert 12 V rail directly to the core voltage required by complex logic chips. A single PWM input signal is all that is required to properly drive the high-side and the low-side MOSFETs. Each driver is capable of driving a 3 nF load at frequencies up to 1 MHz.
Low-Side Driver
Likewise, when the PWM input pin goes low, DRVH will go low after the propagation delay (tpdDRVH). The time to turn off the high-side MOSFET (tfDRVH) is dependent on the total gate charge of the high-side MOSFET. A timer will be triggered once the high-side mosfet has stopped conducting, to delay (tpdhDRVL) the turn on of the low-side MOSFET
Power Supply Decoupling
The low-side driver is designed to drive a ground-referenced low RDS(on) N-Channel MOSFET. The voltage rail for the low-side driver is internally connected to the VCC supply and PGND.
High-Side Driver
The ADP3120A can source and sink relatively large currents to the gate pins of the external MOSFETs. In order to maintain a constant and stable supply voltage (VCC) a low ESR capacitor should be placed near the power and ground pins. A 1 mF to 4.7 mF multi layer ceramic capacitor (MLCC) is usually sufficient.
Input Pins
The high-side driver is designed to drive a floating low RDS(on) N-channel MOSFET. The gate voltage for the high side driver is developed by a bootstrap circuit referenced to Switch Node (SW) pin. The bootstrap circuit is comprised of an external diode, and an external bootstrap capacitor. When the ADP3120A are starting up, the SW pin is at ground, so the bootstrap capacitor will charge up to VCC through the bootstrap diode See Figure 4. When the PWM input goes high, the high-side driver will begin to turn on the high-side MOSFET using the stored charge of the bootstrap capacitor. As the high-side MOSFET turns on, the SW pin will rise. When the high-side MOSFET is fully on, the switch node will be at 12 V, and the BST pin will be at 12 V plus the charge of the bootstrap capacitor (approaching 24 V). The bootstrap capacitor is recharged when the switch node goes low during the next cycle.
Safety Timer and Overlap Protection Circuit
The PWM input and the Output Disable pins of the ADP3120A have internal protection for Electro Static Discharge (ESD), but in normal operation they present a relatively high input impedance. If the PWM controller does not have internal pulldown resistors, they should be added externally to ensure that the driver outputs do not go high before the controller has reached its under voltage lockout threshold. The NCP5381 controller does include a passive internal pulldown resistor on the drive-on output pin.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor (CBST) and the internal (or an external) diode. Selection of these components can be done after the high-side MOSFET has been chosen. The bootstrap capacitor must have a voltage rating that is able to withstand twice the maximum supply voltage. A minimum 50 V rating is recommended. The capacitance is determined using the following equation:
CBST + QGATE DVBST
It is very important that MOSFETs in a synchronous buck regulator do not both conduct at the same time. Excessive shoot-through or cross conduction can damage the MOSFETs, and even a small amount of cross conduction will cause a decrease in the power conversion efficiency. The ADP3120A prevent cross conduction by monitoring the status of the external mosfets and applying the appropriate amount of "dead-time" or the time between the turn off of one MOSFET and the turn on of the other MOSFET. When the PWM input pin goes high, DRVL will go low after a propagation delay (tpdlDRVL). The time it takes for the low-side MOSFET to turn off (tfDRVL) is dependent on the total charge on the low-side MOSFET gate. The ADP3120A monitor the gate voltage of both MOSFETs and the switchnode voltage to determine the conduction status of the MOSFETs. Once the low-side MOSFET is turned off an internal timer will delay (tpdhDRVH) the turn on of the high-side MOSFET
where QGATE is the total gate charge of the high-side MOSFET, and DVBST is the voltage droop allowed on the high-side MOSFET drive. For example, a NTD60N03 has a total gate charge of about 30 nC. For an allowed droop of 300 mV, the required bootstrap capacitance is 100 nF. A good quality ceramic capacitor should be used. The bootstrap diode must be rated to withstand the maximum supply voltage plus any peak ringing voltages that may be present on SW. The average forward current can be estimated by:
IF(AVG) + QGATE fMAX
where fMAX is the maximum switching frequency of the controller. The peak surge current rating should be checked in-circuit, since this is dependent on the source impedance of the 12 V supply and the ESR of CBST.
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ADP3120A
OD VOD_LO tpdlOD 90% DRVH or DRVL 10% tpdhOD VOD_HI
Figure 2. Output Disable Timing Diagram
VPWM_HI IN VPWM_LO tpdlDRVL 90% 2V 10% tpdhDRVH DRVH-SW 10% 2V 10% tpdhDRVL SW trDRVH 90% tpdlDRVH 90% tfDRVH 10% trDRVL tfDRVL 90%
DRVL
Figure 3. Nonoverlap Timing Diagram
12 V
12 V
ADP3120A
4
Output Enable PWM in
BST DRVH 3 SW OD DRVL 2 IN PGND Vcc
1 8 7 5 6
Vout
Figure 4. ADP3120A Example Circuit
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ADP3120A
PACKAGE DIMENSIONS
DFN8 3x3, 0.5P CASE 506BJ-01 ISSUE O
D
A B L1 E
EDGE OF PACKAGE
L
PIN 1 REFERENCE
2X
OPTIONAL CONSTRUCTION
DETAIL A
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D2 E E2 e K L L1 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 1.64 1.84 3.00 BSC 1.35 1.55 0.50 BSC 0.20 --- 0.30 0.50 0.00 0.03
0.10 C
2X
0.10 C
0.05 C
8X
0.05 C
NOTE 4
8X
L
8X
K
E2
8
5
e BOTTOM VIEW
8X
b 0.10 C A B 0.05 C
NOTE 3
SOLDERMASK DEFINED MOUNTING FOOTPRINT
1.85 0.35
8X
3.30
8X
0.63
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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EE EE
CCC CCC CCC
1
L
TOP VIEW
DETAIL B
DETAIL A
OPTIONAL CONSTRUCTION
A (A3) A1
DETAIL A 4
SIDE VIEW D2
C
SEATING PLANE
EXPOSED Cu
MOLD CMPD
DETAIL B
OPTIONAL CONSTRUCTION
1.55
0.50 PITCH
DIMENSION: MILLIMETERS
ADP3120A
PACKAGE DIMENSIONS
SOIC-8 D SUFFIX CASE 751-07 ISSUE AJ
-X- A
8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
B
1
S
4
0.25 (0.010)
M
Y
M
-Y- G
K
C -Z- H D 0.25 (0.010)
M SEATING PLANE
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT*
1.52 0.060
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1
mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
FlexMode is a trademark of Analog Devices, Inc.
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ADP3120A/D

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